Typically, an EEPROM (electrically-erasable-read-only-memory) device includes a polysilicon, floating gate electrode upon which electrical charge is stored. The floating gate electrode overlies a channel region residing between source and drain regions in a semiconductor substrate. The floating gate electrode together with the source, drain and channel regions forms an enhancement transistor. By storing electrical charge on the floating gate electrode, the threshold voltage of the enhancement transistor is brought to a high value. Correspondingly, when charge is removed from the floating gate electrode, the threshold voltage of the enhancement transistor is brought to a relatively low value. The threshold voltage level of the enhancement transistor determines the current flow through the transistor when the transistor is turned on by the application of appropriate voltages to the gate and drain. When the threshold voltage is high, no current will flow through the transistor, which is defined as a logic 0 state. Correspondingly, when the threshold voltage is low, current will flow through the transistor, which is defined as a logic 1 state.
In a flash EEPROM device, electrons are transfered to the floating gate electrode through a dielectric layer overlying the channel region of the enhancement transistor. The electron transfer is initiated by either hot electron injection, or by Fowler-Nordheim tunneling. In either electron transfer mechanism, a voltage potential is applied to the floating gate by an overlying control gate electrode. The control gate electrode is capacitively coupled to the floating gate electrode, such that a voltage applied on the control gate electrode is coupled to the floating gate electrode. The flash EEPROM device is programmed by applying a high positive voltage to the control gate electrode and a lower positive voltage to the drain region, which transfers electrons from the channel region to the floating gate electrode. The flash EEPROM device is erased by grounding the control gate electrode and applying a high positive voltage to either the source or drain region of the enhancement transistor. Under erase voltage conditions, electrons are removed from the floating gate electrode and into either the source or drain regions in the semiconductor substrate.
Individual EEPROM devices are typically arranged in an array, which includes a series of rows and columns. An individual cell resides at the intersection of a row and column and consists of an enhancement transistor and control gate electrode. Advanced EEPROM memory cells also include a select gate electrode overlying a portion of the channel region adjacent to the floating gate electrode. An EEPROM device which includes a select gate electrode and a control gate electrode overlying the channel region of the enhancement transistor is known in the art as a split-gate device. As the demand for increased performance continues, memory designers are increasingly employing split-gate cell designs to improve the read stability of EEPROM arrays. The select gate electrode improves performance by regulating programming current and preventing false "on" conditions during read operations.
One example of a split-gate EEPROM device arranged in accordance with the prior art is illustrated in FIG. 1. The EEPROM device includes an N+ source region S and an N+ drain region D formed in a P- semiconductor substrate and defining a channel region therebetween. A stacked gate structure, which includes a control gate CG overlying a floating gate FG resides over a portion of the channel region adjacent to the drain region D. A select gate SG overlies a portion of the channel region adjacent to the source region and also extends over the stacked gate structure.
The EEPROM device is programmed by injecting electrons onto the floating gate electrode from the source using source-side injection. Additionally, the device is erased by either hole injection, or Fowler-Nordheim tunneling of electrons into the drain region.
An example of a memory array arranged in accordance with the prior art employing an EEPROM device, such as the EEPROM device illustrated in FIG. 1, is shown in the schematic diagram of FIG. 2. The memory array is arranged in a cross-point architecture, where the select gate lines are disposed perpendicular to both the control gate lines and the drain lines. In operation, when data is read from cell A, false "on" signals from the memory cells connected to drain D1 and in the same column as cell A are prevented by grounding select gate lines SG1 and SG3. The select gate electrodes also regulate electrical current in the channel region during programming of the memory cells.
In addition to avoiding false on signals, the cross-point array illustrated in FIG. 2 also avoids gate disturbance conditions in adjacent cells during programming of the selected cell A. Since all of the cells in the same column as cell A of the array share the same control gate line and drain line, all the cells in the column experience the same positive voltage levels as cell A during the programming of cell A. By avoiding a large potential difference in the adjacent cells in the same column as cell A, the electric field generated across the dielectric layer of the adjacent cells is minimized. Also, by maintaining a low electric field in adjacent cells during the programming of cell A, inadvertent programming of the adjacent cells is avoided.
While a cross-point memory cell arranged in accordance with the prior art offers improved performance by stabilizing disturbance conditions in unselected cells during programming, reading, and erasing operations, the EEPROM device and array require three separate layers of polysilicon for the fabrication of the array. In addition to added process complexity, the fabrication of a cross-point array requiring three layers of polysilicon limits the applicability of this array for use as an on-board memory unit in a microprocessor or microcontroller device. Many high performance microprocessors and microcontrollers are designed to be fabricated using only two layers of polysilicon. Accordingly, further development is necessary to provide a cross-point EEPROM array, which fully benefits from the advantages of a split-gate and cross-point architecture.